1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, a method of manufacturing a semiconductor device including salicide process.
2. Description of the Prior Art
Progress in high integration and high speed of semiconductor devices has been remarkable in recent years and thus it has been facilitated to enjoy high speed three dimensional image processing, high speed communication, etc. by a personal computer or a game machine at home. Such high performance can be attained by miniaturizing a CMOS device simply in size. Current CMOS devices whose gate length is about 0.35 .mu.m have been in a mass-production stage, while CMOS devices whose gate length is 0.1 to 0.05 .mu.m have been reported at a research level. However, in such devices that a gate length becomes shorter than 0.35 .mu.m, parasitic resistances which do not meet a scaling rule are increased so that performance cannot be improved along conventional trends. Such a process that gate, source and drain regions are simultaneously formed as silicides to lower their resistances, i.e., a salicide (self-align silicide) process has become indispensable technology.
In the MOS transistor, increase in resistance of a diffusion layer is caused if the diffusion layer is made shallow to suppress the short channel effect. Therefore, such a technology has been examined that a surface of polysilicon constituting the gate electrode and surfaces of the source layer and the drain layer are formed as the silicides in a self-alignment manner to reduce their resistances. TiSi.sub.2, CoSi.sub.2, NiSi, or the like may be used as the silicide.
Next, ordinary manufacturing steps for the MOS transistor in which Co salicide is applied to surface layers of the gate, source, and drain electrodes will be explained.
First, as shown in FIG. 1A, a surface of a region of a silicon substrate 101 isolated by a LOCOS oxide film 102 is thermally oxidized to thereby form a gate oxide film 103 of an about 50 .ANG. thickness. In turn, a polysilicon film 104 of an about 1500 .ANG. thickness is formed on an overall surface by the CVD method.
Then, as shown in FIG. 1B, after any one of boron, phosphorous, and arsenic is ion-implanted into the polysilicon film 104, a gate electrode 105 is formed by patterning the polysilicon film 104. Thereafter, shallow impurity injection layers 106 are formed by ion-implanting phosphorous, for example.
Next, a silicon oxide film of an about 1000 .ANG. thickness is formed by the CVD method and then anisotropic etching is carried out until an upper surface of the gate electrode 105 is exposed. As shown in FIG. 1C, the silicon oxide films remain on both side surfaces of the gate electrode 105 to be utilized as side walls 107.
After this, and after deep impurity injection layers 108 are formed by ion-implanting phosphorous, the shallow impurity injection layers 106 and the deep impurity injection layers 108 are activated by annealing process. As a result, the source layer (109) and the drain layer (110) are formed on both sides of the gate electrode 105 in the silicon substrate 101 as a LDD structure.
Subsequently, after silicon oxide films (natural oxide films) formed on surfaces of the gate electrode 105, the source layer 109 and the drain layer 110 are removed by buffered hydrogen fluoride, as shown in FIG. 1D, a cobalt film 111 of an about 100 .ANG. thickness and a titanium nitride film 112 of an about 300 .ANG. thickness are formed and then silicide formation is executed by RTA (rapid thermal annealing) process at 550.degree. C. for 30 seconds to form cobalt silicide layers 113.
Then, as shown in FIG. 1E, by removing the titanium nitride film 112 and the unreacted cobalt film 111 and executing RTA process at 850.degree. C. for 30 seconds, cobalt silicide layers 113 formed on the gate electrode 105, the source layer 109 and the drain layer 110 are made to have further low resistance.
Such salicide technology is a basic manufacturing step. As improved technologies for the salicide technology, planarization technology for the silicide layer has been disclosed in Patent Application Publication (KOKAI) 62-33466 and film thickness uniformization technology for the silicide layer has been set forth in Patent Application Publication (KOKAI) 5-291180.